AES instruction set
Advanced Encryption Standard Instruction Set (or the Intel Advanced Encryption Standard New Instructions; AES-NI) is an extension to the x86 instruction set architecture for microprocessors from Intel and AMD proposed by Intel in March 2008.[1] The purpose of the instruction set is to improve the speed of applications performing encryption and decryption using the Advanced Encryption Standard (AES).
Contents
[hide]New instructions[edit]
Instruction | Description[2] |
---|---|
AESENC |
Perform one round of an AES encryption flow |
AESENCLAST |
Perform the last round of an AES encryption flow |
AESDEC |
Perform one round of an AES decryption flow |
AESDECLAST |
Perform the last round of an AES decryption flow |
AESKEYGENASSIST |
Assist in AES round key generation |
AESIMC |
Assist in AES Inverse Mix Columns |
PCLMULQDQ |
Carryless multiply (CLMUL)[3] |
Intel and AMD x86 architecture[edit]
The following processors support the AES-NI instruction set:
- Intel[4]
- Intel Westmere based processors, specifically:
- Intel Westmere-EP (Xeon 56xx) (a.k.a. Gulftown Xeon 5600-series DP server model) processors.
- Intel Clarkdale processors (except Core i3, Pentium and Celeron).
- Intel Arrandale processors (except Celeron, Pentium, Core i3, Core i5-4XXM).
- Intel Sandy Bridge processors:
- Intel Ivy Bridge processors.
- All i5, i7, Xeon and i3-2115C[9] only.
- Intel Haswell processors (all except i3-4000m,[10] Pentium and Celeron).
- Intel Broadwell processors (all except Pentium and Celeron).
- Intel Silvermont/Airmont processors (all except Bay Trail-D and Bay Trail-M).
- Intel Skylake processors.
- Intel Kaby Lake processors.
- Intel has a list of processors that support AES-NI on their website.[11]
- Intel Westmere based processors, specifically:
- AMD
- AMD Bulldozer-based processors.[12]
- AMD Piledriver-based processors.
- AMD Steamroller-based processors and successors (Excavator).
- AMD Jaguar-based processors.
- AMD Puma-based processors.
- AMD Zen-based processors.
Hardware acceleration in other architectures[edit]
AES support with unprivileged processor instructions is also available in the latest SPARC processors (T3, T4, T5, M5, and forward) and in latest ARM processors. The SPARC T4 processor, introduced in 2011, has user-level instructions implementing AES rounds.[13] These instructions are in addition to higher level encryption commands. The ARMv8-A processor architecture, announced in 2011, including the ARM Cortex-A53 and A57 (but not previous v7 processors like the Cortex A5, 7, 8, 9, 11, 15[citation needed]) also have user-level instructions which implement AES rounds.[14] In August 2012, IBM announced[15] that the forthcoming Power7+ architecture would have AES support. The commands in these architectures are not directly compatible with the AES-NI commands, but implement similar functionality.
IBM z9 or later mainframe processors support AES as single-opcode (KM, KMC) AES ECB/CBC instructions via IBM's CryptoExpress hardware[16] These single-instruction AES versions are therefore easier to use than Intel NI ones, but may not be extended to implement other algorithms based on AES round functions (such as the Whirlpool hash function).
Supporting x86 CPUs[edit]
VIA x86 CPUs, AMD Geode, and Marvell Kirkwood (ARM, mv_cesa in Linux) use driver-based accelerated AES handling instead. (see Crypto API (Linux))
The following chips, while supporting AES hardware acceleration, do not support the AES-NI instruction set:
ARM architecture[edit]
- Allwinner
- A10, A20, A30, A31, A80, A83T, H3 and A64 using Security System[22]
- Broadcom
- BCM5801/BCM5805/BCM5820 using Security Processor[19]
Other architectures[edit]
- Atmel XMEGA[23] (on-chip accelerator with parallel execution, not an instruction)
- SPARC T3 and later processors have hardware support for several crypto algorithms, including AES.
- Cavium Octeon MIPS[24] All Cavium Octeon MIPS-based processors have hardware support for several crypto algorithms, including AES using special coprocessor 3 instructions.
Performance[edit]
In AES-NI Performance Analyzed, Patrick Schmid and Achim Roos found, "... impressive results from a handful of applications already optimized to take advantage of Intel's AES-NI capability".[25] A performance analysis using the Crypto++ security library showed an increase in throughput from approximately 28.0 cycles per byte to 3.5 cycles per byte with AES/GCM versus a Pentium 4 with no acceleration.[26][27]
Supporting software[edit]
Most modern compilers can emit AES instructions.
Much security and cryptography software supports the AES instruction set, including the following core infrastructure:
- Cryptography API: Next Generation (CNG) (requires Windows)[28]
- Linux's Crypto API
- Java 7 HotSpot
- Network Security Services (NSS) version 3.13 and above[29] (used by Firefox and Google Chrome)
- Solaris Cryptographic Framework[30] on Solaris 10 onwards
- FreeBSD's OpenCrypto API (aesni(4) driver)[31]
- OpenSSL 1.0.1 and above[32]
- FLAM®/FLUC® 5.1.08 (released 2015-08-24) and above
See also[edit]
- Advanced Vector Extensions (AVX)
- CLMUL instruction set
- FMA instruction set (FMA3, FMA4)
- RdRand
References[edit]
- Jump up ^ "Intel Software Network". Intel. Archived from the original on 7 April 2008. Retrieved 2008-04-05.
- Jump up ^ Shay Gueron (2010). "Intel Advanced Encryption Standard (AES) Instruction Set White Paper". Intel. Retrieved 2012-09-20.
- Jump up ^ "Carry-Less Multiplication". Intel.
- Jump up ^ ARK: Advanced Search
- Jump up ^ AnandTech - The Sandy Bridge Review: Intel Core i7-2600K, i5-2500K and Core i3-2100 Tested
- Jump up ^ Compare Intel® Products
- Jump up ^ AES-NI support in TrueCrypt (Sandy Bridge problem)
- Jump up ^ "Some products can support AES New Instructions with a Processor Configuration update, in particular, i7-2630QM/i7-2635QM, i7-2670QM/i7-2675QM, i5-2430M/i5-2435M, i5-2410M/i5-2415M. Please contact OEM for the BIOS that includes the latest Processor configuration update.".
- Jump up ^ [1]
- Jump up ^ http://ark.intel.com/products/75104/Intel-Core-i3-4000M-Processor-3M-Cache-2_40-GHz
- Jump up ^ ARK: Advanced Search
- Jump up ^ "Following Instructions". AMD. November 22, 2010. Archived from the original on November 26, 2010. Retrieved 2011-01-04.
- Jump up ^ Dan Anderson (2011). "SPARC T4 OpenSSL Engine". Oracle. Retrieved 2012-09-20.
- Jump up ^ Richard Grisenthwaite (2011). "ARMv8-A Technology Preview" (PDF). ARM. Retrieved 2012-09-20.
- Jump up ^ Timothy Prickett Morgan (2012). "All the sauce on Big Blue's hot chip: More on Power7+". The Register. Retrieved 2012-09-20.
- Jump up ^ "IBM System z10 cryptography". IBM. Retrieved 2014-01-27.
- Jump up ^ "AMD Geode™ LX Processor Family Technical Specifications". AMD.
- Jump up ^ "VIA Padlock Security Engine". VIA. Retrieved 2011-11-14.
- ^ Jump up to: a b Cryptographic Hardware Accelerators on OpenWRT.org
- Jump up ^ "VIA Eden-N Processors". VIA. Retrieved 2011-11-14.
- Jump up ^ "VIA C7 Processors". VIA. Retrieved 2011-11-14.
- Jump up ^ Security System driver status
- Jump up ^ "Using the XMEGA built-in AES accelerator" (PDF). Retrieved 2014-12-03.
- Jump up ^ "Cavium Networks Launches Industry's Broadest Line of Single and Dual Core MIPS64®-based OCTEON™ Processors Targeting Intelligent Next Generation Networks". Retrieved 2016-09-17.
- Jump up ^ P. Schmid and A. Roos (2010). "AES-NI Performance Analyzed". Tom's Hardware. Retrieved 2010-08-10.
- Jump up ^ T. Krovetz, W. Dai (2010). "How to get fast AES calls?". Crypto++ user group. Retrieved 2010-08-11.
- Jump up ^ "Crypto++ 5.6.0 Pentium 4 Benchmarks". Crypto++ Website. 2009. Archived from the original on 19 September 2010. Retrieved 2010-08-10.
- Jump up ^ "Intel Advanced Encryption Standard Instructions (AES-NI)". Intel. March 2, 2010. Archived from the original on 7 July 2010. Retrieved 2010-07-11.
- Jump up ^ "AES-NI enhancements to NSS on Sandy Bridge systems". 2012-05-02. Retrieved 2012-11-25.
- Jump up ^ "System Administration Guide: Security Services, Chapter 13 Solaris Cryptographic Framework (Overview)". Oracle. September 2010. Retrieved 2012-11-27.
- Jump up ^ "FreeBSD 8.2 Release Notes". FreeBSD.org. 2011-02-24. Retrieved 2011-12-18.
- Jump up ^ OpenSSL: CVS Web Interface[permanent dead link]
External links[edit]
- Intel® Advanced Encryption Standard Instructions (AES-NI)
- AES instruction set whitepaper (4.4 Mbyte, pdf) // Intel